Increasingly wireless systems are evaluated on their power consumption capabilities. A low-power consumption wireless system is highly desired since this generally translates directly to a longer battery life of a wireless device or power consumption in general of the wireless system. Phased Locked Loop (PLL) systems are no exception. Some of the metrics to evaluate PLLs are power consumption and low-jitter noise. It is highly desired to have low-power consumption and low-jitter noise PLLs and even more so for Internet of Things (IoT) systems. Accordingly, there is a need in the art for a PLL with low-power consumption and low-jitter noise for IoT devices and systems of chip (SoC).